About Me:
HEAR IT FROM ME
Welcome to my personal blog. My Name is Dinesh, i started my career as Electrical and Electronic Engineer. However i wasn't very much in power generation/distribution, i liked more of electronics. I have always been keen towards computer architecture and design of computer systems as whole. As much as i like design of computers, i love boxing and fitness. Im a big fan of boxing/MMA and also boxer since last 3 years. No matter what, i spend sometime training myself 4-5days every week. I believe being fit gives you confident, helps you think faster, makes you more independent, Just makes you feel better.
I believe in productivity rather than working for hours. i mean, working in efficient way produces better result. I always followed thing during my hard time , " You can Either have result or Excuse but not Both! " . At points this quote made me give up on my sleep but not on my results. i like the taste of success it is more like addiction to drug, once you feel it you want it.
Talking about my hobbies, i'm also a big gamer. I love to play MMORPG at my free times. At point i was manager of private server. Im not really very much into single player games, it kinda bores me out i like interactive games. Apart from which, i'm very social, i love to meet people from different countries, i like to learn different culture, i like to travel more thought i haven't much so far, i like to eat like beast and workout.
PROJECTS
COMPLEX DESIGN VERIFICATION
This Coursework deals with Couple of Project
1-Perl And Python Scripting to develop Explicit Verilog RTl/Testbench For Shift Registers
This project is all about generating Verilog RTL/Testbench for Shift registers. The information about width, stages and reset value in shift register is provided by the user explicitly. The program needs to detect the input and generate the RTL and Testbench respectively with appropriate values. Then the generated RTL is tested with the testbench, the number of test cases passed over the RTL is 100times the stages. For example if shift register has 16 stages, 1600 random input is passed to check its functionality.
This explicit piece of code is written both in perl and python.
2- Development of Testing Environment in System Verilog to test : ( On-Going )
DESIGN OF COMPUTER ARCHITECTURE
This is on-going project
The project deals with design of 32 bit RISC processor of type Harvard, 14 bit instruction.
As of now, ALU, MEMORY UNIT, INSTRUCTION SETS have been tested
Assembler is created in Python.
DESIGN OF DIGITAL SYSTEM
This course is really awesome. The instructor name is Mark. A. Indovina.
There were 3 projects in this course,
1: Design of CMOS standard cell in Cadence Virtuoso using generic 45nm process technology.
This project is all about CMOS design for various combinations of basic gates. Design of inverter, NAND, NOR, XOR, 2input OAI (OR-AND-INVERTER) and Transmission 2:1 multiplexer is designed in this project. This is done using a 45nm CMOS technology in the cadence virtuoso. The software provides an excellent
base to test the design in user defined way considering the rules that has to be followed for ideal design. The ultimate aim of the project is to provide knowledge regarding the issues faced in designing a CMOS
circuit with respect to various factors from start of design until the desired output is reached. The
technology used is 45nm which provides the limitation to size of transistors that apparently leads to
scaling them down. Once the layout is designed, the variation in rise/fall time can be computed which
directly shows how fast the design was made. It also gives a chance to compare the switching time for
different combination of circuits
2: Design of Hierarchical unit in cadence virtuoso GXL design environment and testing using BSC.
The project 2 is very interesting and has very good link with project 1. It is more
of hierarchical design where the cells made are combined as a single block to work
on a complex function. It gives a good knowledge how the standard cells functions
can be combined together to get a complex function and makes the understanding
in easier way.
The Routing technique is introduced in this project. Router is a tool which is used to
route the connections between the pins automatically. Routing is done to reduce
the complexity of the designing a block and also to reduce the connection space
between the pins. Router is a great tool and does an excellent job except in some
cases where the manual connection is better than router tool. Overall routing done
by router is generally pretty good.
Design done in this project includes
Full adder
D-Flip Flop
TIEHI/TIELO
ADD16
BSC
BSR
BSSUM
BSTEST
Coming to the hierarchical part, this project not only shows how the hierarchical
design is done but also shows few advantages of it and the reason behind this
project.
-The hierarchical block once designed can also be used in other circuit as a
single block which drives as a small part of that circuit.
-Simply saying, it can be reused.
- For instance, in this project the BSC is done using the DFF and TMUX. The
instance of BSC is reused in BSR and BSSUM
- Hierarchical design of bigger circuit reduces the complexity of calculating the
number of cells required, as it only consists of blocks where the blocks
consist of unit cells interconnected between them.
- This reduces the connection between them and reduces the wire spacing
which apparently reduces the delay in signal.
- It is also easy to debug and find which part of circuit is causing error.
3: RTL -FSM - DTMF receiver:
The project is all about working in the bottom level of DTMF receiver. Dual tone multi frequency (DTMF) is a type of in-band signaling. In-band signaling is one of the methods used in transmitting information in network entities. DTMF is generally used in telephones to detect the key that has been pressed. This project gives clear idea about how the received signal is being processed in TDSP to find what key has been pressed. In this project, RTL (register transfer level) module is designed for memory access bus arbiter and this module is used in the DTMF model.
Every key is pre-defined with a set of low-frequency and high-frequency. Every time a key is pressed it generated a spectrum which is fed as input to the DTMF receiver. The DTMF receiver figures what frequency the spectrum has and determines what key has been pressed. To determine the frequency DTMF uses a modified version of discrete fourier algorithm called as goertzel algorithm. In this project,
- A module for memory access bus arbiter is modeled.
- Test vectors are created to test the memory access bus arbiter for few definitions.
- The modeled ARB is then placed into the DTMF block.
- Assembly language is used to execute few statements.
- SPI mode test bench is modeled that stops the simulation when “#” is detected.
- Logic synthesis, timing analysis, gate level verification is done.
ADVANCED DIGITAL SYSTEM
System Level Design of a Multi-channel ADPCM Codec using Single Resource Co-processor:
This is Top down approach SOC project. The ultimate aim of the project is to reduce the bandwidth of the signal that is being transmitted. This was done in few ways before but then the accuracy and the quality of the signal on the receiver is not appreciable. Little other technique evolved over time but then showed ADPCM which used the difference in the signal and transmits the bits, which consumes less bandwidth but also provides decent quality. The other technique and the evolution of them Is discussed in theory part. Adaptive differential pulse code modulation is a technique for speech compression. The ultimate idea is to reduce the bandwidth of the signal that should be transmitted. This paper talks about how hardware and software is implemented to do this. This is a direct hardware where the description is followed; the hardware is fixed point arithmetic to do the computation for 32 channels Encoder/Decoder
COMMUNICATION BETWEEN MULTI CORE CHIPS:
Course Work:
Gives adequate amount of knowledge about multi core chips and focus more on how communication is done between cores. Testing and verification of chips are studied, real time issues and real time scenario is take into picture
Project : Design of NOC Routers
This project deals with design of routers as network on chips. The communication between the chips is done using this routers. Routers, reduce the delay in communication and also reduces the size of buses used. The routers are designed to route the packets to corresponding destination. RTL for routers is written and verified. More information and test results are provided in my paper which can be found in link
REAL TIME EMBEDDED SYSTEMS
There are several projects done using STM32 kit, includes hardware level modification and development of applications. QNX is used to develop some top level application. This is a group project coded by me and my teammate. Entire work does not belong individually to either of us, but both of us.
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